Implement Synthesizable Square Root Algorithm On Fpga Engineering Essay

Implement Synthesizable Squ atomic number 18 Root Algorithm On Fpga Engineering EssayThe main objective of this paper is to implement synthesizable determine parentage algorithmic program on FPGA. As straight root function is not synthesizable on Silicon, this paper proposes optimized non restoring square root algorithm for unsigned 8 function anatomy on ED2C20F484C7 device in Cyclone II family. This algorithm is employ in gate level abstraction of Verilog HDL. The basic building block of the design is CSM (Controlled reckon Multiplex) block. It makes use of only subtract exertion and append 01 which is an improvement over restoring algorithm.Keyword FPGA,CSM,Verilog HDL,fixed pointIntroductionThe square root function is a basic operation in computer graphic and scientific calculation application. Due to its algorithm complexity, the square root operation is hard to be designed in digital system. As known, digital system has been used in daily life or industrial purpose that may have been in need of square root operation to fully execute its functions. Scientists have developed various algorithms for square root calculation. But the execution of algorithms is difficult because of their complexities and thus imparts into long delays for its completion. in that respect are two main families of algorithms that poop be used to extract square roots. The first-class honours degree family is that of digit recurrence, which provides one digit (often one patch) of the result at each iteration6. Each iteration consists of additions and digit-by-number multiplications (which have comparable cost)Such algorithms have been widely used in microprocessors that didnt include hardware multipliers. Most of the FPGA implementations in vendor tools or in the literature use this approach. Second family of algorithms uses multiplications. It includes quadratic convergence recurrences derived from the Newton-Raphson iteration 5. The digit recurrence approaches allow one to build minimal hardware, magical spell multiplicative approaches allow one to make the best use of available resources when these include multipliers. Also there are estimation method and digit-by-digit method. Digit-by-digit method is assort into two distinct classes restoring and non- restoring algorithm 1.In restoring algorithm, remainder is restored in the regular flow. So its implementation needs more hardware. Compared to the restoring algorithm, the non restoring algorithm does not restore the remainder, which can be implemented with fewest hardware resource and the result is hardware simple implementation. It is most suitable for FPGA implementation.Restoring and non restoring square root calculationRestoring Algorithm shade 1 If it is a 2n bit number then divide it in a group of 2 bitsStep2 Subtract 1 from the first 2 digits (starting from MSB)Step3 Whenever the result of the subtraction is positive then the developed root is 1 otherwise 0Step4 Whenever the result is negative, save up it as it is. We have to restore the wrong meditation by appending01 and guessed square root.Step5 Now take the succeeding(a)(a) two digitsStep6 Append 01 (to be subtracted from next two digits of dividend) and guessed square root tosubtract from the remainder.Step7 If the result of subtraction is negative then restore previous remainder by adding wrong guess byappending 01 and guessed square root.Step8 Every time guessed square root has to be updated while appending 01.Step9 Continue the steps until the group of two digits end1 0 0 1.1 0 1 001 01 11 01.00 00 00 00 0100 01 take next two digits from dividend 1 01 Append 01Negative value 11 00+ 1 010 0 01 11-10 0111 10 Negative value+ 10 0101 11 01 10 00 0111 00 00 10 01 0101 01 1 0010011 011011111+ 1001101010110 00 010011001000010111 00 1001101011100100111Figure 1 The example of restoring algorithm to solve square rootB. Proposed Modified Non Restoring AlgorithmA little modification in non restoring algorithm ma kes calculation faster. It uses only subtract operation and appends 01. It uses n stage pipelining to find square root of 2n bit number. The following algorithm describes the modified non restoring square root algorithm.Step1 StartStep2 Initialize the radicand (p) which is 2n bit number. Divide the radicand in two bits beginning atbinary point in both directions.Step3 Beginning on the left (most significant), select the first group of one or two digit (If n is oddthen first group is one digit ,else two bits)Step4 Select the first group of bits and subtract 01 from it. If bor actors line is zero, result is positive andquotient is 1 else it is 0.Step5 Append 01(to be subtracted next two digits of dividend) and guessed square root to subtractfrom remainder of previous stageStep6 If result of subtraction is negative, write previous remainder as it is and quotient is considered as0, else write the difference as remainder and quotient as 1.Step7 Repeat step 5 and step 6 until end group of two digits.Step8 End1 0 0 1.1 0 1 001 01 11 01.00 00 00 00 00 0100 01 take next two digits from dividend 1 01 Append 0111 10 0101 11 01100 0111 00 001001 01001011 00100110100101100 00 100110010000010111 00100110101001011100Figure 2 The example of modified non restoring algorithm to solve square rootBasic Building Block for Non restoring algorithmInputs of the building block are x,y,b and u while d and b0(borrow) are outputs.If b0=0, then db0=( x .y)+(b.x)+(by)d= (x.y.b.u)+(x.y.b.u)+(xy.b)+(x.u)+(x.y.b)csmblock.jpgFigure 3 RTL schematic of CSM blockThe generalization of simple implementation of non restoring digit by digit algorithm for unsigned 6 bit square root by array structure is shown in Fig.4. Each row of the circuit executes one iteration of non restoring digit by digit square algorithm, where it only uses subtract operation and appends 01.Figure 4 Pipelined structure of 6 bit unsigned square root numberThe design can be optimized by minimizing the logic expressions and can be implemented by modifying CSM block. The specialized entities A,B,C,D,E,F,G and H are derived from CSM block and are defined as followsFor csmA, ybu = 100b0 = xd = xFor csmB, yu = 00b0 = x.bd = x.b + b.xFor csmC, u = 0b0 = x.y + x.b + y.bd = x.y.b + x.y.b + x.y.b + x.y.bFor csmD, yb = 10b0 = xd = x.u + x.uFor csmE, y = 0b0 = x.bd = x.b.u + b.x + x.uFor csmF, xy = 00b0 = bd = b.uFor csmG, xyb = 010b0 = xd = uFor csmH, xyu = 000b0 = bFigure 5 Optimized Pipelined structure of 8 bit unsigned square root numberResults and analysisThe Non Restoring algorithm can be implemented with least hardware resources and the result will be the faster than restoring square rooting techniques. The source code is implemented in such a manner that it can be extended according to users requirement to calculate complicated square root in FPGA.Figure 6 Simulation result of 8 bit square root using non restoring algorithmThe DE1 kit has 4 7 segment displays only so the maximum number which can be displa yed is 9999d and also it doesnt have a decimal point. Hence output obtained is less precise if one of the displays is considered as a decimal point.Table 1 shows the contention of Logic Elements usage for 8 bit implementation. This indicates the size of theimplemented circuit hardware resource.Table 1 Comparison of LEs usage in 8 bit implementationNoImplementation of non restoring algorithm for 8 bitLEs18 bit (with seven segment)8528 bit (without seven segment)713optimized 8 bit (with seven segment)644optimized 8 bit (without seven segment)50Table 2 PowerPlay Power analyzer StatusNoPowerPlay Power Analyzer Status8 bit with optimization (mW)8 bit without optimization (mW)LowMediumLow1Total Thermal Power Dissipation71.65447.9672.842Core Dynamic Thermal Power Dissipation0190.4703Core placid Thermal Power Dissipation47.3648.0647.364I/O Thermal Power Dissipation24.29209.4425.48ConclusionThis implementation and analysis shows that proposed method is most effectual of hardware resource . This is reasonable, because it only uses subtract operation and append 01. The result shows that the proposed algorithm is easy to implement and also uses less resources. The result is extended for square root implementation of 8 bit floating point number and also it can be expanded to larger numbers to solve complicated square root problem in FPGA implementation.